Binary Addition Circuits

Addition and Subtraction are two basic Arithmetic Operations that must be performed by any Digital Computer. If both these operations can be properly implemented, then Multiplication and Division tasks become easy (as multiplication is repeated addition and division is repeated subtraction).

Consider the operation of adding two binary numbers, which is one of the fundamental tasks performed by a digital computer. The four basic addition operations two single bit binary numbers are:

• 0 + 0 = 0
• 1 + 0 = 1
• 0 + 1 = 1
• 1 + 1 = (Carry)1 0

In the first three operations, each binary addition gives sum as one bit , i.e., either 0 or 1. But for the fourth addition operation (where the inputs are 1 and 1), the result consists of two binary digits. Here, the lower significant bit is called as the ‘Sum Bit’, while the higher significant bit is called as the ‘Carry Bit’.

For single bit additions, there may not be an issue. The problem may arise when we try to add binary numbers with more than one bit.

The logic circuits which are designed to perform the addition of two binary numbers are called as Binary Adder Circuits. Depending on how they handle the output of the ‘1+1’ addition, they are divided into:

• Half Adder
• Full Adder

Let us take a look at the binary addition performed by various adder circuits.

Half Adder

A logic circuit used for adding two 1-bit numbers or simply two bits is called as a Half Adder circuit. This circuit has two inputs and two outputs. The inputs are the two 1-bit binary numbers (known as Augend and Addend) and the outputs are Sum and Carry.

The following image shows the block diagram of Half Adder.

The truth table of the Half Adder is shown in the following table.

If we observe the ‘Sum’ values in the above truth table, it resembles an Ex-OR Gate. Similarly, the values for ‘Carry’ in the above truth table resembles an AND Gate.

So, to properly implement a Half Adder, you need two Logic Gates: an XOR gate for ‘Sum’ Output and an AND gate for ‘Carry’ output. The following image shows the Logic Diagram of a Half Adder.

In the above half adder circuit, inputs are labeled as A and B. The ‘Sum’ output is labeled as summation symbol (∑) and the Carry output is labeled with C_O.

Half adder is mainly used for addition of augend and addend of first order binary numbers i.e., 1-bit binary numbers. We cannot add binary numbers with more than one bit as the Half Adder cannot include the ‘Carry’ information from the previous sum.

Due to this limitation, Half Adder is practically not used in many applications, especially in multi-digit addition. In such applications, carry of the previous digit addition must be added along with two bits; hence it is a three bit addition.

Full Adder

A Full Adder is a combinational logic circuit which performs addition on three bits and produces two outputs: a Sum and a Carry. As we have seen that the Half Adder cannot respond to three inputs and hence the full adder is used to add three digits at a time.

It consists of three inputs, of which two are input variables representing the two significant bits to be added,  whereas the third input terminal is the carry from the previous addition. The two outputs are a Sum and Carry outputs.

The following image shows a block diagram of a Full Adder where the inputs are labelled as A, B and C_IN, while the outputs are labelled as ∑ and C_OUT.

Coming to the truth table, the following table shows the truth table of a Full Adder.

From the above truth table, we can obtain the Boolean Expressions for both the Sum and Carry Outputs. Using those expressions, we can build the logic circuits for Full Adder. But by simplifying the equations further, we can derive at a point that a Full Adder can be easily implemented using two Half Adders and an OR Gate.

The following image shows a Full Adder Circuit implemented using two Half Adders and an OR Gate. Here, A and B are the main input bits, C_IN is the carry input, ∑ and C_OUT are the Sum and Carry Outputs respectively.

Parallel Binary Adders

As we discussed, a single Full Adder performs the addition of two one bit numbers and also the carry input. For performing the addition of binary numbers with more than one bit, more than one full adder is required and the number of Full Adders depends on the number bits. Thus, a Parallel Adder, is a combination of Multiple Full Adders and is used for adding all bits of the two numbers simultaneously.

By connecting ‘n’ number of full adders in parallel, an n-bit Parallel Adder can be constructed. From the below figure, it is to be noted that there is no carry at the least significant position, hence we can use either a half adder or make the carry input of full adder as zero at this position.

The following figure shows a Parallel 4-bit Binary Adder, which has three full adders and one half adder. The two binary numbers to be added are  ‘A₃ A₂ A₁ A₀‘  and  ‘B₃ B₂ B₁ B₀‘ , which are applied to the corresponding inputs of the Full Adders. This parallel adder produces their result as  ‘C₄ S₃ S₂ S₁ S₀‘ , where C₄ is the final carry.

In the 4 bit adder, first block is a half-adder that has two inputs as A₀ B₀ and produces a sum S₀ and a carry bit C₁. The first block can also be a full adder and if so, then the input Carry C₀ must be 0.

Next three blocks should be full adders, as there are three inputs applied to them (two main binary bits and a Carry bit from the previous stage).

Hence, the second block full adder produces a sum S₁ and a carry C₂. This will be followed by other two full adders and thus the final result is C₄ S₃ S₂ S₁ S₀.

Commonly, the Full Adders are designed in dual in-line package integrated circuits. 74LS283 is a popular 4-bit full adder IC. Arithmetic and Logic Unit or ALU of an unit computer consist of these parallel adders to perform the addition of binary numbers.

Binary Subtraction Circuits

Another basic arithmetic operation to be performed by Digital Computers is the Subtraction. Subtraction is a mathematical operation in which one integer number is deducted from another to obtain the equivalent quantity. The number from which other number is to be deducted is called as ‘Minuend’ and the number subtracted from the minuend is called ‘Subtrahend’.

Similar to the binary addition, binary subtraction is also has four possible basic operations. They are:

• 0 – 0 = 0
• 0 – 1 = (Borrow)1 1
• 1 – 0 = 1
• 1 – 1 = 0

The above figure shows the four possible rules or elementary operations of the binary subtractions. In all the operations, each subtrahend bit is deducted from the minuend bit.

But in the second rule, minuend bit is smaller than the subtrahend bit, hence 1 is borrowed to perform the subtraction. Similar to the adder circuits, basic subtraction circuits are also of two types:

• Half Subtractor
• Full Subtractor

Half Subtractors

A Half Subtractor is a multiple output Combinational Logic Circuit that does the subtraction of two 1-bit binary numbers. It has two inputs and two outputs. The two inputs correspond to the two 1-bit binary numbers and the two outputs corresponds to the Difference bit and Borrow bit (in contrast to Sum and Carry in Half Adder).

The following image shows the block diagram of a Half Subtractor.

Image

Following table shows the truth table of a Half Subtractor.

From the above truth table, we can say that the ‘Difference’ output of the Half Subtractor is similar to an XOR output (which is also same as the Sum output of the Half Adder). Thus, the Half Subtraction is also performed by the Ex-OR gate with an AND gate with one inverted input and one normal input, requiring to perform the Borrow operation.

The following image shows the logic circuit of a Half Adder.

This circuit is similar to that of the Half Adder with only difference being the minuend input i.e., A is complemented before applied at the AND gate to implement the borrow output.

In case of multi-digit subtraction, subtraction between the two digits must be performed along with borrow of the previous digit subtraction, and hence a subtractor needs to have three inputs, which is not possible with a Half Subtractor. Therefore, a half subtractor has limited set of applications and strictly speaking, it is not used in practice.

Full Subtractor

A Full Subtractor is a combinational logic circuit which performs a subtraction between the two 1-bit binary numbers and it also considers the borrow of the previous bit i.e., whether 1 has been borrowed by the previous minuend bit.

So, a Full Subtractor has three inputs, in which two inputs corresponding to the two bits to be subtracted (minuend A and subtrahend B), and a borrow bit, usually represented as B_IN, corresponding to the borrow operation. There are two outputs, one corresponds to the difference D output and the other Borrow output B_O.

The following image shows the block diagram of a full subtractor.

The following table shows the truth table of a Full Subtractor.

By deriving the Boolean expression for the full subtractor from above truth table, we get the expression that tells that a full subtractor can be implemented with half subtractors with OR gate as shown in figure below.

By comparing the adder and subtractor circuits and truth tables, we can observe that the output D in the full subtractor is exactly same as the output S of the full adder. And the only difference is that input variable A is complemented in the full subtractor.

Therefore, it is possible to convert the full adder circuit into full subtractor by simply complementing the input A before it is applied to the gates to produce the final borrow bit output Bo.

Parallel Binary Subtractors

To perform the subtraction of binary numbers with more than one bit, we have to use the Parallel Subtractors. This parallel subtractor can be designed in several ways, including combination of half and full subtractors, all full subtractors, all full adders with subtrahend complement input, etc.

The below figure shows a 4 bit Parallel Binary Subtractor formed by connecting one half subtractor and three full subtractors.

In this subtractor, 4 bit minuend  ‘A₃ A₂ A₁ A₀‘  is subtracted by 4 bit subtrahend  ‘B₃ B₂ B₁ B₀‘  and the result is the difference output  ‘D₃ D₂ D₁ D₀‘ . The borrow output of each subtractor is connected as the borrow input to the next subtractor.

It is also possible to design a 4 bit parallel subtractor using 4 full adders as shown in the below figure. This circuit performs the subtraction operation by considering the principle that the addition of minuend and the complement of the subtrahend is equivalent to the subtraction process.

We know that the subtraction of A by B is obtained by taking 2’s complement of B and adding it to A. The 2’s complement of B is obtained by taking 1’s complement and adding 1 to the least significant pair of bits.

Hence, in this circuit 1’s complement of B is obtained with the inverters (NOT gate) and a 1 can be added to the sum through the input carry.

Parallel Adder / Subtractor

The operations of both addition and subtraction can be performed by a one common binary adder. Such binary circuit can be designed by adding an Ex-OR gate with each full adder as shown in below figure. The figure below shows the 4 bit parallel binary adder/subtractor which has two 4 bit inputs as  ‘A₃ A₂ A₁ A₀‘  and  ‘B₃ B₂ B₁ B₀‘ .

The mode input control line M is connected with carry input of the least significant bit of the full adder. This control line decides the type of operation, whether addition or subtraction.

When M= 1, the circuit is a subtractor and when M=0, the circuit becomes adder. The Ex-OR gate consists of two inputs to which one is connected to the B and other to input M. When M = 0, B Ex-OR of 0 produce B. Then, full adders add the B with A with carry input zero and hence an addition operation is performed.

When M = 1, B Ex-OR of 0 produce B complement and also carry input is 1. Hence the complemented B inputs are added to A and 1 is added through the input carry, nothing but a 2’s complement operation. Therefore, the subtraction operation is performed.

Conclusion

A complete beginner’s tutorial on Binary Adders and Subtractors. You learned different binary adder circuits like Half Adder, Full Adder, Parallel Adder and different binary subtractors like Half Subtractor, Full Subtractor, Parallel Subtractor and also a Combination Parallel Adder / Subtractor circuit.

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Introduction

In the previous tutorial, we learned about Multiplexers or simply MUX. Multiplexers are simple combinational logic circuit, which selects one of many inputs and passes it through the single output. MUX is the device responsible for Multiplexing.

The action or operation of a Demultiplexer is exactly the opposite to that of a Multiplexer. As an inverse to the MUX, Demux is a one-to-many circuit. With the use of a Demultiplexer, data from one input can be passed to one of the many output data lines.

Demultiplexers are mainly used in Boolean function generators and decoder circuits. Different input/output configuration demultiplexers are available in the form of single integrated circuits (ICs).

Also, there is a facility of cascading two or more DEMUX circuits, to generate multiple output demultiplexers. Let us get a brief idea of demultiplexers and its types in this tutorial.

What is a Demultiplexer?

The process of getting information from one input and transmitting the same over one of many outputs is called Demultiplexing. If you recall the Multiplexer tutorial, there we discussed the concept of Multiplexing. Demultiplexing is just the opposite of that.

A Demultiplexer is a combinational logic circuit that receives the information on a single input line and transmits the same information over one of ‘n’ possible output lines.

In order to select a particular output, we have to use a set of Select Lines and the bit combinations of these select lines control the selection of specific output line to be connected to the input at a given instant. The below figure illustrates the basic idea of demultiplexer, in which the switching of the input to any one of the four outputs is possible at a given instant.

If Multiplexers are called as Data Selectors, then Demultiplexers are called as Data Distributors, since they transmit the same data which is received at the input to different destinations.

Thus, a demultiplexer is a 1-to-N device, where as the multiplexer is an N-to-1 device. The figure below shows the block diagram of a demultiplexer or simply a DEMUX.

It consists of 1 input line, ‘n’ output lines and ‘m’ select lines. In this, m select lines are required to produce 2^m possible output lines (consider 2^m = n). For example, a 1-to-4 demultiplexer requires 2 (2² = 4) select lines to control the 4 output lines.

There are several types of demultiplexers based on the output configurations such as 1:2, 1:4, 1:8 and 1:16.

These are available in different IC packages and some of the most commonly used demultiplexer ICs includes 74139 (dual 1:4 DEMUX), 74138 (1:8 DEMUX), 74237 (1:8 DEMUX with Address Latches), 74154 (1:16 DEMUX), 74159 (1:16 DEMUX open collector type), etc.

NOTE: The Demultiplexer ICs are also called as Decoder ICs. For example, 74159 is a 4-line to 16-line Decoder IC.

1-to-2 Demultiplexer

A 1-to-2 demultiplexer consists of one input line, two output lines and one select line. The signal on the select line helps to switch the input to one of the two outputs. The figure below shows the block diagram of a 1-to-2 demultiplexer with additional enable input.

In the figure, there are only two possible ways to connect the input to output lines, thus only one select signal is enough to do the demultiplexing operation. When the select input is LOW, then the input will be passed to Y0 and if the select input is HIGH, then the input will be passed to Y1.

The truth table of a 1-to-2 demultiplexer is shown below, in which the input is routed to Y0 and Y1 depending on the value of select input S.

We can derive the Boolean Expressions for the outputs as follows:

Assume S is the Select Input, D is the Data Input and Y0 and Y1 are the outputs of the 1-to-2 Demultiplexer. From the above table, the output Y0 is active when the combination of select line and input line are active low and high respectively, i.e.,  S D = 0 1 .

Therefore, the expression for output Y0 is

 Y0 = S D 

Similarly, the output Y1 is active when the combination of select line and input line are active high, i.e.,  S D = 1 1 .

Therefore, the expression for output Y0 is

 Y1 = S D 

From the above truth table and the derived Boolean Expressions, the logic diagram of 1-to-2 demultiplexer can be designed using two AND gates and one NOT gate as shown in below figure. When the select line S = 0, the first AND gate (A1) is enabled, while the second AND gate (A2) is disabled.

Then, the data from the input flows to the output line Y0. Similarly, when S = 1, the second AND gate (A2) is enabled and the first AND gate (A1) is disabled, thus data is passed to the Y1 output.

1-to-4 Demultiplexer

A 1-to-4 demultiplexer has a single input (D), two selection lines (S1 and S0) and four outputs (Y0 to Y3). The input data goes to any one of the four outputs at a given time for a particular combination of select lines.

This demultiplexer is also called as a 2-to-4 Demultiplexer, which means that it has two select lines and 4 output lines. The block diagram of a 1:4 DEMUX is shown below.

The truth table of this type of demultiplexer is given below. From the truth table it is clear that, when S0 = 0 and S1 = 0, the data input is connected to output Y0 and when S0 = 0 and s1=1, the data input is connected to output Y1.

Similarly, other outputs are connected to the input for the other two combinations of select lines.

From the above truth table, we can derive the Boolean Expressions for the outputs as follows:

 Y0 = S1 S0 D 

 Y1 = S1 S0 D 

 Y2 = S1 S0 D 

 Y3 = S1 S0 D 

Where D is the input data, Y0 to Y3 are output lines and S0 & S1 are select lines.

From the above Boolean expressions, a 1-to-4 demultiplexer can be implemented by using four 3-input AND gates and two NOT gates as shown in figure below. The two select lines enable a particular AND gate at a time. Additionally, there is an Enable / Strobe Input, which acts as a global enable input i.e., the outputs are active only when the ‘E’ bit is HIGH.

So depending on the combination of select inputs, input data is passed through the selected gate to the associated output.

This type of demultiplexer is available in integrated circuit form as IC 74139. It one of the most commonly used demultiplexer ICs and it is a dual 1-to-4 demultiplexer IC i.e., it contains two independent 1-to-4 demultiplexer blocks in one IC.  Each DEMUX accepts two binary inputs as select lines and four mutually exclusive active-low outputs.

Both demultiplexers have individual set of select lines so they can acts as truly independent Demux. Also, each demultiplexer consists of dedicated enable pin, which can act as a data input for the demultiplexer operation. The Enable pins are active LOW.

The outputs are active LOW i.e., they are HIGH by default. So, if the Enable pin is HIGH, all the outputs are HIGH and if Enable is LOW, then based on the Select Pins, only the corresponding output pin becomes LOW.

1-to-8 Demultiplexer

The below figure shows the block diagram of a 1-to-8 demultiplexer that consists of single input D, three select inputs S2, S1 and S0 and eight outputs from Y0 to Y7.

It is also called as 3-to-8 demultiplexer due to its three select input lines and 8 output lines. It distributes one input line to one of 8 output lines depending on the combination of select inputs.

The truth table for 1-to-8 demultiplexer is shown below. The input ‘D’ is connected with one of the eight outputs from Y0 to Y7 based on the select lines S2, S1 and S0.

For example, if S2 S1 S0 = 0 0 0, then the input D is connected to the output Y0 and so on.

From this truth table, the Boolean expressions for all the outputs can be written as follows.

 Y0 = S2 S1 S0 D 

 Y1 = S2 S1 S0 D 

 Y2 = S2 S1 S0 D 

 Y3 = S2 S1 S0 D 

 Y4 = S2 S1 S0 D 

 Y5 = S2 S1 S0 D 

 Y6 = S2 S1 S0 D 

 Y7 = S2 S1 S0 D 

From these obtained equations, the logic diagram of this demultiplexer can be implemented by using eight 4-input AND gates and three NOT gates as shown in below figure. Different combinations of the select lines activates one AND gate at given time, such that data input will appear at the corresponding output.

There are two popular 1-to-8 demultiplexer integrated circuits. One is the IC 74237, that consists of latches at three select inputs. The pin out of this IC is given below.

The pins A0 to A2 are data inputs, Y0 to Y7 are demultiplexer outputs, E1&E2 are active-low data enable and active-high data enable pins respectively, LE is the latch enable input ,Vcc and GND terminals are positive supply voltage and ground terminals.

This IC combines a 3-bit storage latch with the 3-to-8 decoder function.

Another commonly used 1-to-8 demultiplexer integrated circuits is the IC 74138. The pinout is very similar except that there is no Latch Enable input (as all the enable pins are normal enable pins – two are active LOW and one is active HIGH) and the outputs are active LOW. The following image shows the pinout of 74138 IC.

1-to-8 DEMUX using Two 1-to- 4 Demultiplexers

When the application requires a higher order demultiplexer with more number of output pins, then we cannot implement by a single integrated circuit. In case if more than 16 output pins are needed, then two or more demultiplexer ICs are cascaded to fulfill the requirement.

For example, if the application needs 32 output lines from a DEMUX, then we cascade two 1:16 demultiplexers or three 1:8 demultiplexers. Therefore, by cascading the two or more demultiplexers, a large demultiplexer can be implemented.

Consider the case that a 1-to-8 demultiplexer can be implemented by using two 1-to-4 demultiplexers with a proper cascading.

In the above figure, the highest significant bit A of the selection inputs are connected to the enable inputs such that it is complemented before connecting to one DEMUX and to the other it is directly connected.

By this configuration, when A is set to zero, one of the output lines from Y0 to Y3 is selected based on the combination of select lines B and C. Similarly, when A is set to one, based on the select lines one of the output lines from Y4 to Y7 will be selected.

Implementation of Full Subtractor Using 1-to-8 DEMUX

Similar to the multiplexers, demultiplexers are also used for Boolean function implementation as well as combinational circuit design. We can design a demultiplexer to produce any truth table output by properly controlling the select lines.

Consider the case for implementing a demultiplexer circuit in order to produce the full subtractor output. The truth table below shows the output of a full subtractor.

From the above table, the full subtractor output D can be written as

 D = f (A, B, B_IN) 

 D = ∑m (1, 2, 4, 7) 

 D = A B B_IN + A B B_IN + A B B_IN + A B B_IN 

And the borrow output can be expressed as

 B_OUT = f (A, B, B_IN) = ∑m (1, 2, 3, 7) 

 B_OUT = A B B_IN + A B B_IN + A B B_IN + A B B_IN 

From these Boolean expressions, a demultiplexer for producing full subtractor output can be built by properly configuring the 1-to-8 DEMUX, such that with input D = 1, it gives the minterms at the output.

And by logically ORing these minterms, the outputs of difference and borrow can be obtained as shown in figure.

Applications of Demultiplexer

Since the demultiplexers are used to select or enable the one signal out of many, these are extensively used in microprocessor or computer control systems such as:

• Selecting different IO devices for data transfer (Data Routing)
• Choosing different banks of memory (Memory Decoding)
• Depends on the address, enabling different rows of memory chips
• Enabling different functional units.

Other than these, demultiplexers can be found in a wide variety of application such as:

• Synchronous data transmission systems
• Boolean function implementation (as we discussed full subtractor function above)
• Data acquisition systems
• Combinational circuit design
• Automatic test equipment systems
• Security monitoring systems (for selecting a particular surveillance camera at a time), etc.

Conclusion

A complete beginner’s guide on Demultiplexers or DEMUX. You learned what is a Demultiplexer, different types of Demux like 1-to-2, 1-to-4, 1-to-8, 1-to-16, their logic circuits and some important applications of Demultiplexers.

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What is Multiplexing?

Multiplexing is the process of combining one or more signals and transmitting on a single channel. In analog communication systems, a communication channel is a scarce quantity, which must be properly used. For cost-effective and efficient use of a channel, the concept of Multiplexing is very useful as it allows multiple users to share a single channel in a logical way.

The three common types of Multiplexing approaches are:

• Time
• Frequency
• Space

Two of the best examples of Multiplexing Systems used in our day-to-day life are the landline telephone network and the Cable TV.

The device which is responsible for Multiplexing is known as Multiplexer. Multiplexers are used for both Analog and Digital signals. Let us focus on digital signals in this tutorial, to keep things simple. A multiplexer is the most frequently used combinational circuit and it is an important building block in many in digital systems.

These are mostly used to form a selected path between multiple sources and a single destination. A basic multiplexer has various data input lines and a single output line. These are found in many digital system applications such as data selection and data routing, logic function generators, digital counters with multiplexed displays, telephone network, communication systems, waveform generators, etc. In this article we are going to discuss about types of multiplexers and its design.

What is a Multiplexer?

The multiplexer or MUX is a digital switch, also called as data selector. It is a Combinational Logic Circuit with more than one input line, one output line and more than one select line. It accepts the binary information from several input lines or sources and depending on the set of select lines, a particular input line is routed onto a single output line.

The basic idea of multiplexing is shown in figure below in which data from several sources are routed to the single output line when the enable switch is ON. This is why, multiplexers are also called as ‘many to one’ combinational circuits.

The below figure shows the block diagram of a multiplexer consisting of n input lines, m selection lines and one output line. If there are m selection lines, then the number of possible input lines is 2^m. Alternatively, we can say that if the number of input lines is equal to 2^m, then m selection lines are required to select one of n (consider 2^m = n) input lines.

This type of multiplexer is referred to as 2ⁿ × 1 multiplexer or 2ⁿ-to-1 multiplexer. For example, if the number of input lines is 4, then two select lines are required. Similarly, to select one of 8 input lines, three select lines are required.

Generally, the number of data inputs to a multiplexer is a power of two such as 2, 4, 8, 16, etc. Some of the most frequently used multiplexers include 2-to-1, 4-to-1, 8-to-1 and 16-to-1 multiplexers.

These multiplexers are available in IC forms with different input and select line configurations. Some of the available multiplexer ICs include 74157 (Quad 2-to-1 MUX), 78158 (Quad 2-to-1 MUX with inverse output), 74153 (4-to-1 MUX), 74152 (8-to-1 MUX) and 74150 (16-to-1 MUX).

2-to-1 Multiplexer

A 2-to-1 multiplexer consists of two inputs D0 and D1, one select input S and one output Y. Depending on the select signal, the output is connected to either of the inputs. Since there are two input signals, only two ways are possible to connect the inputs to the outputs, so one select is needed to do these operations.

If the select line is low, then the output will be switched to D0 input, whereas if select line is high, then the output will be switched to D1 input. The figure below shows the block diagram of a 2-to-1 multiplexer which connects two 1-bit inputs to a common destination.

The truth table of the 2-to-1 multiplexer is shown below. Depending on the value of the select input, the inputs i.e., D0, D1 are produced at outputs. The output is D0 when Select value is S = 0 and the output is D1 when Select value is S = 1.

‘X’ in the above truth table denotes a don’t care condition. So, ignoring the don’t care conditions, we can derive the Boolean Expression of a typical 2 to 1 Multiplexer as follows:

 Y = SD0 + SD1 

From the above output expression, the logic circuit of 2-to-1 multiplexer can be implemented using logic gates as shown in figure. It consists of two AND gates, one NOT gate and one OR gate. When the select line, S=0, the output of the lower AND gate is zero, but the output of upper AND gate is D0. Thus, the output generated by the OR gate is equal to D0.

Similarly, when S=1, the output of the upper AND gate is zero, but the output of lower AND gate is D1. Therefore, the output of the OR gate is D1. Thus, the above given Boolean expression is satisfied by this circuit.

In order to efficiently use the Silicon, IC Manufacturers fabricate multiple Multiplexers in a single IC. Generally four 2 line to 1 line multiplexers are fabricated in a single IC. Some of the popular ICs of 2 to 1 multiplexers include IC 74157 and IC 74158.

Both these ICs are Quad 2-to-1 Multiplexers. While IC 74157 has a normal output, the IC74158 has an inverted output. There is only one selection line, which controls the input lines to the output in all four multiplexers.

The output Y0 can be either A0 or B0 depending on the status of the select line. Similarly, Y1 can be either A1 or B1, Y2 can be either A2 or B2 and so on. There is an additional Strobe or Enable control input E/Strobe, which enables and disables all the multiplexers, i.e., when E=1, outputs of all the multiplexer is zero irrespective of the value of S.

All the multiplexers are activated only when the E / Strobe input is LOW.

4-to-1 Multiplexer

A  4-to-1 multiplexer consists four data input lines as D0 to D3, two select lines as S0 and S1 and a single output line Y. The select lines S0 and S1 select one of the four input lines to connect the output line. The figure below shows the block diagram of a 4-to-1 multiplexer in which, the multiplexer decodes the input through select line.

The truth table of a 4-to-1 multiplexer is shown below in which four input combinations 00, 10, 01 and 11 on the select lines respectively switches the inputs D0, D2, D1 and D3 to the output. That means when S0=0 and S1 =0, the output at Y is D0, similarly Y is D1 if the select inputs S0=0 and S1= 1 and so on.

From the above truth table, we can write the output expressions as follows:

 Y = S0 S1 D0 + S0 S1 D1 + S0 S1 D2 + S0 S1 D3 

From the above expression of the output, a 4-to-1 multiplexer can be implemented by using basic logic gates. The below figure shows the logic circuit of 4:1 MUX which is implemented by four 3-inputs AND gates, two 1-input NOT gates, and one 4-inputs OR gate.

In this circuit, each data input line is connected as input to an AND gate and two select lines are connected as other two inputs to it. Additionally, there is also an Enable Signal. The output of all the AND gates are connected to inputs of OR gate in order to produce the output Y.

Generally, this type of multiplexers is available in IC with dual mode i.e., there will be two 4-to-1 Multiplexers in a single IC. The most common and popular 4-to-1 line multiplexer is IC 74153 which, is a dual 4-to-1 line multiplexer. It consists of two identical 4-to-1 multiplexers. It has two separate enable or strobe inputs to switch ON or OFF the individual multiplexers. But the Select lines are common to both the Multiplexers.

Usually, the enable input or strobe can be used to cascade two or more multiplexer ICs to construct a multiplexer with large number of inputs. Each multiplier is supplied with separate inputs. The figure below shows the pin diagram of IC74153.

8-to-1 Multiplexer

An 8-to-1 multiplexer consists of eight data inputs D0 through D7, three input select lines S0 through S2 and a single output line Y. Depending on the select lines combinations, multiplexer selects the inputs.

The below figure shows the block diagram of an 8-to-1 multiplexer with enable input that can enable or disable the multiplexer. Since the number data bits given to the MUX are eight, then 3 bits (2³ = 8) are needed to select one of the eight data bits.

The truth table for an 8-to1 multiplexer is given below with eight combinations of inputs so as to generate each output corresponds to input.

For example, if S2= 0, S1=1 and S0=0 then the data output Y is equal to D2. Similarly the data outputs D0 to D7 will be selected through the combinations of S2, S1 and S0 as shown in below figure.

From the above truth table, the Boolean equation for the output is given as:

 Y = S0 S1 S2 D0 + S0 S1 S2 D1 + S0 S1 S2 D2 + S0 S1 S2 D3 + S0 S1 S2 D4 + S0 S1 S2 D5 + S0 S1 S2 D6 + S0 S1 S2 D7 

From the above Boolean equation, the logic circuit diagram of an 8-to-1 multiplexer can be implemented by using 8 AND gates, 1 OR gate and 7 NOT gates as shown in below figure. In the circuit, when enable pin is set to one, the multiplexer will be disabled and if it is zero, then select lines will select the corresponding data input to pass through the output.

IC 74151 is a popular 8-to-1 multiplexer IC with eight inputs and two outputs. The two outputs are active low and active high outputs. It has three select lines A, B and C and one active low enable input. The pinout of this IC is given below.

8-to-1 Mux using 4-to-1 Mux and 2-to-1 Mux

If you observe the Boolean Expression of 8-to-1 Multiplexer shown above, we can re-write it as follows:

 Y = S0 S1 S2 D0 + S0 S1 S2 D1 + S0 S1 S2 D2 + S0 S1 S2 D3 + S0 S1 S2 D4 + S0 S1 S2 D5 + S0 S1 S2 D6 + S0 S1 S2 D7 

 Y = S0 (S1 S2 D0 + S1 S2 D1 + S1 S2 D2 + S1 S2 D3) + S0( S1 S2 D4 + S1 S2 D5 + S1 S2 D6 + S1 S2 D7) 

The expression in the first bracket i.e.,  S1 S2 D0 + S1 S2 D1 + S1 S2 D2 + S1 S2 D3  is similar to the Boolean Expression of a 4-to-1 Multiplexer with D0, D1, D2 and D3 as inputs and S1 and S2 as Select Lines. Let this expression be P1.

Similarly, the expression in the second bracket i.e.,  S1 S2 D4 + S1 S2 D5 + S1 S2 D6 + S1 S2 D7  is similar to the Boolean Expression of another 4-to-1 Multiplexer with D4, D5, D6 and D7 as inputs and S1 and S2 as Select Lines. Let this expression be P2.

Now, replacing the above expressions with P1 and P2, we get,

 S0 P1 + S0 P2 

This expression is similar to a 2-to-1 Multiplexer with P1 and P2 (where, P1 and P2 are outputs of respective 4-to-1 Multiplexers) as Inputs and S0 as Select Signal. So, finally, we can deduce that an 8-to-1 Multiplexer can be implemented using two 4-to-1 Multiplexers and one 2-to-1 Multiplexer. The block diagram of the same is shown below:

16-to-1 Multiplexer

All the higher order Multiplexers like 8-to-1, 16-to-1, etc. can be implemented using lower order multiplexers. But none-the-less, let us take a quick look at 16-to-1 Multiplexer. IC 74150 is a popular 16-to-1 Multiplexer IC. The inputs to a 16-to-1 MUX are D0, D1, D2 and so on up tp D15. Since it has 16 input lines, there will be 4 select lines namely S0, S1, S2 and S3.

The following image shows the block diagram of a typical 16-to-1 Multiplexer.

Simplified truth table for 16×1 Multiplexer is shown in the following table.

The Boolean Expression of a 16-to-1 Multiplexer is as follows:

 Y = S0 S1 S2 S3 D0 + S0 S1 S2 S3 D1 + S0 S1 S2 S3 D2 + S0 S1 S2 S3 D3 + S0 S1 S2 S3 D4 + S0 S1 S2 S3 D5 + S0 S1 S2 S3 D6 + S0 S1 S2 S3 D7 + S0 S1 S2 S3 D8 + S0 S1 S2 S3 D9 + S0 S1 S2 S3 D10 + S0 S1 S2 S3 D11 + S0 S1 S2 S3 D12 + S0 S1 S2 S3 D13 + S0 S1 S2 S3 D14 + S0 S1 S2 S3 D15 

The following image shows the logical circuit of a 16-to-1 Multiplexer.

Similar to an 8-to-1 Multiplexer, we can implement 16-to-1 Multiplexer using lower order multiplexers like 8-to-1, 4-to-1 and 2-to-1. The following image shows the block diagram of a 16-to-1 Multiplexer implemented using two 8-to-1 Multiplexers and one 2-to-1 Multiplexer.

Further, we can implement the individual 8-to-1 Multiplexers in the above image using two 4-to-1 Multiplexers and one 2-to-1 Multiplexer.

Application of Multiplexer

In all types of digital system applications, multiplexers find its immense usage. Since these allows multiple inputs to be connected independently to a single output, multiplexers are found in variety of applications including data routing, logic function generators, control sequencers, parallel-to-serial converters, etc.

Data Routing

Multiplexers are extensively used in data routing applications to route the data to a one particular destination from one of several sources. One of the applications includes the displaying of two multidigit BCD counters, one at a time. In such application, 74157 multiplexer ICs are used to select and display the content of either of two BCD counters using a set of decoder and LED displays.

Logic Function Generator

In place of logic gates, a logical expression can be generated by using a multiplexer. It is possible to connect the multiplexer such that it duplicates the logic of any truth table. In such cases it can generate the Boolean algebraic function of a set of input variables.

This abruptly reduces the number of logic gates or integrated circuits to perform the logic function since the multiplexer is a single integrated circuit. In this kind of applications, multiplexers are viewed as logic function generators.

For example consider the below logic diagram to implement the ex-OR function of three inputs. A 74151A 8-to-1 multiplexer is used in this logic generator. This multiplexer works exactly similar to the set of logic gates implementing the same function.

The output F is 1 for data inputs D1, D2, D5 and D6 which are selected by making selection lines to 001, 010, 100 and 111 respectively.

Parallel to Serial Conversion

A multiplexer circuit can be used to convert the parallel data to serial data in order to reduce the number of parallel buses by converting them to serial signals. This type of conversion is needed in telecommunication, test and measurement, military/aerospace, data communications applications.

Mostly in digital systems, data is processed in parallel for achieving higher speeds. But for transmission of the data signals over long distances, we need more number of lines. In such cases, parallel data is converted into serial form using multiplexers.

The figure below shows the parallel to serial data conversion using an 8 input multiplexer. Parallel data from the data in or some other register is applied to the 8 input lines of the multiplexer.

The selection codes for the multiplexer are generated by a 3-bit counter. With the application of each clock pulse to the counter the data is serially out from the multiplexer.

Other applications of multiplexers include control sequencers, pulse train generators, encoders, register to register data transfer, waveform generators, etc.

Conclusion

Complete tutorial on Multiplexer (MUX) and Multiplexing. You learned the basics of Multiplexing, multiplexer, different types of commonly used multiplexers like 2:1 MUX, 4:1 MUX, 8:1 MUX and 16:1 MUX, their Boolean Expressions, logic circuits and also couple of important applications of Multiplexers.

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The simplest of errors is corruption of a bit i.e., a 1 may be transmitted as a 0 or vice-versa. To confirm whether the received data is the intended data or not, we should be able to detect errors at the receiver.

In this tutorial, we will learn about Parity Bit, Even Parity, Odd Parity, Parity Generator and Parity Checker with a practical example and practical circuit.

What is Parity Bit?

The parity generating technique is one of the most widely used error detection techniques for the data transmission. In digital systems, when binary data is transmitted and processed, data may be subjected to noise so that such noise can alter 0s (of data bits) to 1s and 1s to 0s.

Hence, a Parity Bit is added to the word containing data in order to make number of 1s either even or odd. The message containing the data bits along with parity bit is transmitted from transmitter to the receiver.

At the receiving end, the number of 1s in the message is counted and if it doesn’t match with the transmitted one, it means there is an error in the data. Thus, the Parity Bit it is used to detect errors, during the transmission of binary data.

Parity Generator and Checker

A Parity Generator is a combinational logic circuit that generates the parity bit in the transmitter. On the other hand, a circuit that checks the parity in the receiver is called Parity Checker. A combined circuit or device of parity generators and parity checkers are commonly used in digital systems to detect the single bit errors in the transmitted data.

Even Parity and Odd Parity

The sum of the data bits and parity bits can be even or odd. In even parity, the added parity bit will make the total number of 1s an even number, whereas in odd parity, the added parity bit will make the total number of 1s an odd number.

The basic principle involved in the implementation of parity circuits is that sum of odd number of 1s is always 1 and sum of even number of 1s is always 0. Such error detecting and correction can be implemented by using Ex-OR gates (since Ex-OR gate produce zero output when there are even number of inputs).

To produce two bits sum, one Ex-OR gate is sufficient whereas for adding three bits, two Ex-OR gates are required as shown in below figure.

Parity Generator

It is combinational circuit that accepts an n-1 bit data and generates the additional bit that is to be transmitted with the bit stream. This additional or extra bit is called as a Parity Bit.

In even parity bit scheme, the parity bit is ‘0’ if there are even number of 1s in the data stream and the parity bit is ‘1’ if there are odd number of 1s in the data stream.

In odd parity bit scheme, the parity bit is ‘1’ if there are even number of 1s in the data stream and the parity bit is ‘0’ if there are odd number of 1s in the data stream. Let us discuss both even and odd parity generators.

Even Parity Generator

Let us assume that a 3-bit message is to be transmitted with an even parity bit. Let the three inputs A, B and C are applied to the circuit and output bit is the parity bit P. The total number of 1s must be even, to generate the even parity bit P.

The figure below shows the truth table of even parity generator in which 1 is placed as parity bit in order to make all 1s as even when the number of 1s in the truth table is odd.

The K-map simplification for 3-bit message even parity generator is

From the above truth table, the simplified expression of the parity bit can be written as

The above expression can be implemented by using two Ex-OR gates. The logic diagram of even parity generator with two Ex – OR gates is shown below. The three bit message along with the parity generated by this circuit which is transmitted to the receiving end where parity checker circuit checks whether any error is present or not.

To generate the even parity bit for a 4-bit data, three Ex-OR gates are required to add the 4-bits and their sum will be the parity bit.

Odd Parity Generator

Let us consider that the 3-bit data is to be transmitted with an odd parity bit. The three inputs are A, B and C and P is the output parity bit. The total number of bits must be odd in order to generate the odd parity bit.

In the given truth table below, 1 is placed in the parity bit in order to make the total number of bits odd when the total number of 1s in the truth table is even.

The truth table of the odd parity generator can be simplified by using K-map as

The output parity bit expression for this generator circuit is obtained as

P = A ⊕ (B ⊕ C)

The above Boolean expression can be implemented by using one Ex-OR gate and one Ex-NOR gate in order to design a 3-bit odd parity generator.

The logic circuit of this generator is shown in below figure, in which two inputs are applied at one Ex-OR gate, and this Ex-OR output and third input is applied to the Ex-NOR gate, to produce the odd parity bit. It is also possible to design this circuit by using two Ex-OR gates and one NOT gate.

Parity Check

It is a logic circuit that checks for possible errors in the transmission. This circuit can be an even parity checker or odd parity checker depending on the type of parity generated at the transmission end. When this circuit is used as even parity checker, the number of input bits must always be even.

Even Parity Checker

Consider that three input message along with even parity bit is generated at the transmitting end. These 4 bits are applied as input to the parity checker circuit, which checks the possibility of error on the data. Since the data is transmitted with even parity, four bits received at circuit must have an even number of 1s.

If any error occurs, the received message consists of odd number of 1s. The output of the parity checker is denoted by PEC (Parity Error Check).

The below table shows the truth table for the Even Parity Checker in which PEC = 1 if the error occurs, i.e., the four bits received have odd number of 1s and PEC = 0 if no error occurs, i.e., if the 4-bit message has even number of 1s.

The above truth table can be simplified using K-map as shown below.

The above logic expression for the even parity checker can be implemented by using three Ex-OR gates as shown in figure. If the received message consists of five bits, then one more Ex-OR gate is required for the even parity checking.

Odd Parity Checker

Consider that a three bit message along with odd parity bit is transmitted at the transmitting end. Odd parity checker circuit receives these 4 bits and checks whether any error are present in the data.

If the total number of 1s in the data is odd, then it indicates no error, whereas if the total number of 1s is even then it indicates the error since the data is transmitted with odd parity at transmitting end.

The below figure shows the truth table for odd parity generator where PEC =1 if the 4-bit message received consists of even number of 1s (hence the error occurred) and PEC= 0 if the message contains odd number of 1s (that means no error).

The expression for the PEC in the above truth table can be simplified by K-map as shown below.

After simplification, the final expression for the PEC is obtained as

PEC = (A Ex-NOR B) Ex-NOR (C Ex-NOR P)

The expression for the odd parity checker can be designed by using three Ex-NOR gates as shown below.

Parity Generator/Checker ICs

There are different types of parity generator /checker ICs are available with different input configurations such as 5-bit, 4-bit, 9-bit, 12-bit, etc. One of the most commonly used and standard type of parity generator/checker IC is 74180.

It is a 9-bit parity generator or checker used to detect errors in high speed data transmission or data retrieval systems. The figure below shows the pin diagram of 74180 IC.

This IC can be used to generate a 9-bit odd or even parity code or it can be used to check for odd or even parity in a 9-bit code (8 data bits and one parity bit).

This IC consists of eight parity inputs from A through H and two cascading inputs. There are two outputs even sum and odd sum. In implementing generator or checker circuits, unused parity bits must be tied to logic zero and the cascading inputs must not be equal.

If this IC is used as an Even Parity Checker and when a parity error occurs, the ‘sum even’ output goes low and ‘sum odd’ output goes high. If this IC is used as an Odd Parity Checker, the number of input bits should be odd, but if an error occurs the ‘sum odd’ output goes low and ‘sum even’ output goes high.

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Exclusive-NOR Gate

The operation of Exclusive NOR gate is reciprocal to the Exclusive OR gate’s operation. As the basic AND gate implements the Boolean addition , while OR gate implements Boolean multiplication and NOT implements inversion function , there is no such Boolean function defined by the XNOR.This can be derived by basic gates (AND , OR ,NOT).Below shows the diagram of EX-NOR constructed from EX-OR gate.

The logic symbol and Boolean expression for the XNOR gate is shown below.

Ex – NOR gate Logic Symbol and Boolean expression

There are multiple standards for defining an electronic component. Generally we follow IEC (International Electro-technical Commission) standards and IEEE (Institute of Electrical and Electronics Engineers). The XNOR logic symbol in IEEE and IEC standards is shown below.

It is a Hybrid gate, the Boolean expression of output of XNOR gate is given as below

The XNOR output is represented as

XNOR Truth table

If we observe the operation of XNOR gate, we can say that the XNOR gate output will be HIGH when both the inputs are not same and will become LOW for different combination of input. This we can see in truth table.

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X-NOR Gate using Basic logic gates

If a specific gate is not available directly, we can design the gate by connecting multiple gates together. An EX-NOR gate can be designed by using basic logic gates like NAND gate and NOR gate.

Using NOR Gates

Using NAND Gates

Using NAND and OR Gates

Ex – NOR Gate Pulsed Operation

The pulsed operation of 2 input XOR gate is shown below.

Initially when one of the two inputs of the XNOR gate is low, so the output is at low level. When both the input changes to low level, the XNOR output will rise to HIGH level and again when one of the inputs comes to low level, the output also comes to low level.

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3-input Ex-NOR Gate

We can have XOR gate with more than 2 inputs, in some cases. The Boolean function is same for the 3- input XNOR gate is

3-Input Ex-NOR gate logic symbolTruth table

For Exclusive NOR gates, we can have the HIGH input when even numbers of inputs are at HIGH level. So the 3-input XNOR gate is called as “Even functioned OR gate”.The truth table and logic symbol for 3-input XNOR gate is given below.

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Ex-NOR Function Realization using NOR gates

If A and B are inputs and Q is the output of XNOR gate then

Q= A XNOR B = (A XOR B)’

Q’= (A XOR B) = A’B + AB’ = A’B + AB’ + AA’ + BB’ = (A + B) (A’ + B’)

Q’= A’ (A + B) + B’ (A + B)

Take compliment

Q= (A’ (A + B) + B’ (A + B))’ = (A’ (A + B) )’ . (B’ (A + B))’ = (A + (A + B)’). (B + (A + B)’)

Take compliment again

Q’= ( (A + (A + B)’). (B + (A + B)’) )’ = (A + (A + B)’)’ + (B + (A + B)’)’

Take compliment again

Q= [ (A + (A + B)’)’ + (B + (A + B)’)’ ]’

Now we can implement the XNOR circuit using NOR gates

Ex-NOR Function Realization using NAND gates

Q= (A XOR B)’ = (A’B + AB’ = A’B + AB’ + AA’ + BB’)’ = ((A + B) (A’ + B’))’

Now we need to implement this circuit using NAND gates

Q= ( (A + B) (AB)’ )’ = (A . (AB)’ + B. (AB)’)’

Taking compliment

Q’= A. (AB)’ + B. (AB)’ = (A. (AB)’). (B. (AB)’)

Taking compliment again

Q= (A. (AB)’)’. (B. (AB)’)

Now we can implement XNOR gate using NAND gates

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Commonly available TTL and CMOS logic Ex-NOR gate IC’s

Some of the most used XNOR logic ICs are listed below

74266 Quad 2-input Ex-NOR Gate IC

Pin description:

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Ex-NOR gate applications

1. The XNOR logic gates are used in error detecting circuits which are to detect Odd parity or even parity bits in digital data transmission circuits.
2. XNOR gate is mainly used in arithmetic and encryption circuits. This process is the combinational operation of the XOR and XNOR gates, by using 6 transistors for low power application.

This is also used as Heat exchanger tank, which will ring the alarm when the water temperature level goes up or down, to the pre-set level. The Heat exchanger circuit is explained below.

Construction:

This circuit is used to warm the water. It has two outlets and two float indicators. The float indicators are connected as the inputs of XNOR gate. The output of the XNOR gate is connected to the alarm circuit, which used to alert when the water level changes in the glass beaker. There is a heating element at the bottom of the beaker to heat the certain amount of water.

When the water reaches high level, the excess water will overflow from the upper outlet. When the water comes to low level, then the heating element situated at the bottom is not covered by water so it will burn out. As we said earlier, it alerts the when the water level increases or decreases to certain level. To do this, the float switches are to be placed at high level and low level positions of water, inside the tank.

When a float indicator gets in contact with water level, it is pushed upwards. This will cause the float’s leaver to disconnect from the armature. At this situation, the XNOR gate’s input is 0. If the float indicator is not in contact with the water level, then the leaver is connected to +5 V supply, making the armature active. At this situation, the XNOR gate’s input will be HIGH, which is equal to 1. When the 2 leavers are connected to the +5 volts supply or to ground voltage, then the 2 inputs of the XNOR gate is 1, and thus the output of the XNOR gate is high, so that it activates the alarm and alerts the person.

When the water level is between upper floater and lower floater indicator, then logic 1 is applied from upper indicator and logic 0 from lower indicator, to the input of XNOR gate. At this position no alarm will ring as the water level will is at required level. This is how the logic XNOR gate used as a Heat exchanger circuit.

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These are also available in IC form with different bit comparing configurations such as 4-bit, 8-bit, etc. More than one comparator can also be connected in cascade arrangement to perform comparison of numbers of longer lengths.Whenever we want to compare the two binary numbers, first we have to compare the most significant bits.

If these MSBs are equal, then only we need to compare the next significant bits. But if the MSBs are not equal, then it would be clear that either A is greater than or less than B and the process of comparison ceases.

For example, the two 2-bit number are A = A1A0 and B=B1B0. If A1 is not equal to B1, then it is clear that A is greater than B for A1 =1 & B1= 0 or else A is less than B for A0= 0 & B0 =1. At this stage the process of comparison ceases.

If the MSBs are equal, i.e., A1=B1 only then we need to compare the next significant bits A0 and B0 and decide whether the number is greater than, less than or equal. So, the comparator produces three outputs as L, E and G corresponds to less than, equal and greater than comparisons.

Digital comparators can be of two types

Identity Comparator

Comparators that have only one output terminal and produces the output either low or high are identity comparators.

Magnitude Comparator

Comparators with three output terminals and checks for three conditions i.e greater than or less than or equal to is magnitude comparator.

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Digital Comparator

A magnitude digital comparator is a combinational circuit that compares two digital or binary numbers (consider A and B) and determines their relative magnitudes in order to find out whether one number is equal, less than or greater than the other digital number.

Three binary variables are used to indicate the outcome of the comparison as A>B, A<B, or A=B. The below figure shows the block diagram of a n-bit comparator which compares the two numbers of n-bit length and generates their relation between themselves.

These comparators can compare 2-bit, 4-bit and 8-bit numbers depending on the application requirement. These are available in TTL as well as CMOS logic family ICs and some of these ICs include IC 7485 (4-bit comparator), IC 4585 (4-bit comparator in CMOS family) and IC 74AS885 (8-bit comparator).

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Single Bit Magnitude Comparator

A comparator used to compare two bits, i.e., two numbers each of single bit is called a single bit comparator. It consists of two inputs for allowing two single bit numbers and three outputs to generate less than, equal and greater than comparison outputs.

The figure below shows the block diagram of a single bit magnitude comparator. This comparator compares the two bits and produces one of the 3 outputs as L (A<B), E (A=B) and G (A>B).

The truth table for the single bit comparator is given below. When A0 B0 = 00 & 11, both inputs are equal, therefore A=B output will be high. When A0 B0 = 01, B is more than A and hence AB is active.

From the truth table logical expressions for each output can be expressed as

By using these Boolean expressions, we can implement a logic circuit for this comparator using two AND gates, one NOT gate and one Ex-NOR gate as shown in below figure. AND gates are used to find whether a binary digit is less than greater than another bit whereas Ex-NOR gate is used to find whether two binary numbers are equal or not.

In the figure, one AND gate has inputs of A0 (B0) ̅ and another has inputs (A0) ̅ B0. Therefore, one AND gate output is 1 if A0 > B0 (i.e., A0 =1 and B0 =0) and is zero if A0 < B0 (i.e., A0 =0 and B0 =1). Similarly, other AND gate output is one if A0 < B0 (i.e., A0 =0 and B0 =1) and is zero if A0 > B0 (i.e., A0 =1and B0 =0).

The Ex-NOR gate has inputs A0 B0, hence the output of the Ex-NOR gate will be 1 if A0 = B0 and the output will be 0 if A0 is not equal to B0.

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2-Bit Comparator

A 2-bit comparator compares two binary numbers, each of two bits and produces their relation such as one number is equal or greater than or less than the other. The figure below shows the block diagram of a two-bit comparator which has four inputs and three outputs.

The first number A is designated as A = A1A0 and the second number is designated as B = B1B0. This comparator produces three outputs as G (G = 1 if A>B), E (E = 1, if A = B) and L (L = 1 if A<B).The truth table of this comparator is shown below which depicting various input and output states.

The k-map simplification for the above truth table is as follows.

From the above k-map simplification, each output can be expressed as

By using above obtained Boolean equation for each output, the logic diagram can be implemented by using four NOT gates, seven AND gates, two OR gates and two Ex-NOR gates.

The figure below shows the logic diagram of a 2-bit comparator using basic logic gates. It is also possible to construct this comparator by cascading of two 1-bit comparators.

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4-Bit Comparator

It can be used to compare two four-bit words. The two 4-bit numbers are A = A3 A2 A1 A0 and B3 B2 B1 B0 where A3 and B3 are the most significant bits.

It compares each of these bits in one number with bits in that of other number and produces one of the following outputs as A = B, A < B and A>B. The output logic statements of this converter are

• If A3 = 1 and B3 = 0, then A is greater than B (A>B). Or
• If A3 and B3 are equal, and if A2 = 1 and B2 = 0, then A > B. Or
• If A3 and B3 are equal & A2 and B2 are equal, and if A1 = 1, and B1 = 0, then A>B. Or
• If A3 and B3 are equal, A2 and B2 are equal and A1 and B1 are equal, and if A0 = 1 and B0 = 0, then A > B.

From the above statements, the output A > B logic expression can be written as

The equal output is produced when all the individual bits of one number are exactly coincides with corresponding bits of another number. Then the logical expression for A=B output can be written as

E = (A3 Ex-NOR B3) (A2 Ex-NOR B2) (A1 Ex-NOR B1) (A0 Ex-NOR B0)

From the above output Boolean expressions, the logic circuit for this comparator can be implemented by using logic gates as given below. In this the four outputs from Ex-NOR gates are applied to AND gate to give the binary variable E or A = B. The other two outputs are also use Ex-NOR outputs to generate the Boolean functions as shown figure.

The 4-bit comparator is mostly available in IC form and common type of this IC is 7485. This IC can be used to compare two 4-bit binary words by grounding I (A>B), I (A<B) and I (A=B) connector inputs to Vcc terminal. The figure below shows the pin diagram of IC7485 comparator.

In addition to the normal comparator, this IC is provided with cascading inputs in order to facilitate the cascading several comparators. Any number of bits can be compared by cascading several of these comparator ICs.

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8-Bit Comparator

An 8-bit comparator compares the two 8-bit numbers by cascading of two 4-bit comparators. The circuit connection of this comparator is shown below in which the lower order comparator A<B, A=B and A>B outputs are connected to the respective cascade inputs of the higher order comparator.

For the lower order comparator, the A=B cascade input must be connected High, while the other two cascading inputs A ,B must be connected to LOW. The outputs of the higher order comparator become the outputs of this eight-bit comparator.

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Applications of Comparators

• These are used in the address decoding circuitry in computers and microprocessor based devices to select a specific input/output device for the storage of data.
• These are used in control applications in which the binary numbers representing physical variables such as temperature, position, etc. are compared with a reference value. Then the outputs from the comparator are used to drive the actuators so as to make the physical variables closest to the set or reference value.
• Process controllers
• Servo-motor control

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Most often seven-segment displays are used to display the digits in digital watches, calculators, clocks, measuring instruments and digital counters, etc. Generally, LCD and LED segments provide the display output of numerical numbers and characters.

However to display the characters and numbers (in order to produce the decimal readout), seven-segment displays are most commonly used. Mostly these displays are driven by the output stages of digital ICs (to which the visual indication of the output stages has to be performed) such as latches and decade counters, etc.

But these outputs are in the form of 4-bit binary coded decimal (BCD), and not suitable for directly driving the seven-segment displays.

A display decoder is used to convert a BCD or a binary code into a 7 segment code. It generally has 4 input lines and 7 output lines. Here we design a simple display decoder circuit using logic gates.

Even though commercial BCD to 7 segment decoders are available, designing a display decoder using logic gates may prove to be beneficial from economical as well as knowledge point of view.

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Principle of Display Decoder Circuit

The basic idea involves driving a common cathode 7-segment LED display using combinational logic circuit.  The logic circuit is designed with 4 inputs and 7 outputs, each representing an input to the display IC. Using Karnough’s map, logic circuitry for each input to the display is designed.

Related Post: Water Level Indicator using AVR Microcntroller

Theory Behind the Circuit:

The first and foremost aspect of this circuit is decoder. A decoder is a combinational circuit which is used to convert a binary or BCD (Binary Coded Decimal) number to the corresponding decimal number . It can be a simple binary to decimal decoder or a BCD to 7 segment decoder.

Another relevant section is the combinational logic circuitry. A combinational logic circuit is a system of logic gates consisting of only outputs and inputs. The output of a combinational logic circuit depends only on the present state of the inputs and nothing else. Best examples of such circuits are Encoders and Decoders, Multiplexers and De-multiplexers, Adders, Subtractors etc.

To understand the design and operation of these logic circuits, one needs to have a good knowledge about Boolean algebra and logic gates. For example few basic Boolean algebra rules to be followed are the complementary law, associative law, De-Morgan’s law etc.

A 7 segment LED display consists of an arrangement of 8 LEDs such that either all the anodes are common or cathodes are common.  A common cathode 7 segment display consists of 8 pins – 7 input pins labeled from ‘a’ to ‘g’ and 8^th pin as common ground pin.

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7 Segment Display Decoder Circuit Design

Step 1: The first step of the design involves analysis of the common cathode 7-segment display.  A 7-segment display consists of an arrangement of LEDs in an ‘H’ form.  A truth table is constructed with the combination of inputs for each decimal number. For example, decimal number 1 would command a combination of b and c (refer the diagram given below).

Image Resource Link: www.thelearningpit.com

Step 2: The second step involves constructing the truth table listing the 7 display input signals, decimal number and corresponding 4 digit binary numbers.

The truth table for the decoder design depends on the type of 7-segment display. As we mentioned above that for a common cathode seven-segment display, the output of decoder or segment driver must be active high in order to glow the segment.

The figure below shows the truth table of a BCD to seven-segment decoder with common cathode display. In the truth table , there are 7 different output columns corresponding to each of the 7 segments.

Suppose the column for segment a shows the different combinations for which it is to be illuminated. So ‘a’ is active for the digits 0, 2, 3, 5, 6, 7, 8 and 9.

From the above truth table, the Boolean expressions of each output functions can be written as

a = F1 (A, B, C, D) = ∑m (0, 2, 3, 5, 7, 8, 9)

b = F2 (A, B, C, D) = ∑m (0, 1, 2, 3, 4, 7, 8, 9)

c = F3 (A, B, C, D) = ∑m (0, 1, 3, 4, 5, 6, 7, 8, 9)

d = F4 (A, B, C, D) = ∑m (0, 2, 3, 5, 6, 8)

e = F5 (A, B, C, D) = ∑m (0, 2, 6, 8)

f = F6 (A, B, C, D) = ∑m (0, 4, 5, 6, 8, 9)

g = F7 (A, B, C, D) = ∑m (2, 3, 4, 5, 6, 8, 9)

Step 3: The third step involves constructing the Karnough’s map for each output term and then simplifying them to obtain a logic combination of inputs for each output.

K-Map Simplification

The below figures shows the k-map simplification for the common cathode seven-segment decoder in order to design the combinational circuit.

From the above simplification, we get the output values as

Step 4: The final step involves drawing a combinational logic circuit for each output signal. Once the task was accomplished, a combinational logic circuit can be drawn using 4  inputs (A,B,C,D)and a 7- segment display (a,b,c,d,e,f,g) as output.

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Display Decoder Circuit Operation

The circuit operation can be understood through the truth table itself. When all the inputs are connected to low logic , the output of the combinational logic circuit would be so as to drive all the output LEDs except ‘g’ to conduction.  Thus the number 0 will be displayed. Similar operation would take place for all other combinations of the input switches.

Note: Also read the interesting post – LED Blinking Circuits

Practically BCD to 7 segment decoders are available in form of integrated circuits such as 74LS47.  Apart from regular 4 input pins and 7 output pins, it consists of a lamping test pin used for segment testing, ripple blanking input pin used to blank off zeros in multiple display systems, ripple blanking output pin used for cascading purposes and a blanking input pin.

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Applications of Display Decoder Circuit

1. This circuit can be modified using timers and counters to display the number of clock pulses.
2. This circuit can be modified to develop an alphabet display system instead of a decimal number display system.
3. It can be used as a timer circuit.

[Also Read: How To Make an Adjustable Timer ]

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Limitations of Display Decoder Circuit

1. This circuit involves lot of logic gates and is quite complex.
2. Timing delay by each logic gate is a matter of concern and this circuit might not produce accurate results when used to display count of pulses.
3. This is a theoretical circuit and may require few modifications.

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A digital decoder converts a set of digital signals into corresponding decimal code. A decoder is also a most commonly used circuit in prior to the use of encoder. The encoded data is decoded for user interface in most of the output devices like monitors, calculator displays, printers, etc. once after the information is encoded by encoders. In this article we are going to study on different types of binary decoders.

Binary Decoders

A binary decoder is a multi-input, multi-output combinational circuit that converts a binary code of n input lines into a one out of 2n output code. These are used when there is need to activate exactly one of 2n output based on an n-bit input value.

The figure below shows the general structure of binary decoder in which encoded information is accepted at n input lines and the output is produced at 2n possible output lines.

Generally, decoders are provided with enable inputs so as to activate the decoded output based on data inputs. As an example, in case of BCD code, the 4 bit combinations from 0000 through 1001 are enough to represent the decimal digits 0 to 9.

Depending on the number of input lines, the inputs of a binary code can be 2-bit or 3-bit or 4-bit codes. Upon the availability of 2n lines, it activates the one of its output by deactivating (making logic 0) all other input whenever it receives n inputs.

Usually the number of bits in output code is more than the bits in its input code. The most commonly used practical binary decoders are 2-to-4 decoder, 3-to-8 decoder and 4-to-16 line binary decoder.

2-to-4 Binary Decoder

In a 2-to-4 binary decoder, two inputs are decoded into four outputs hence it consists of two input lines and 4 output lines. Only one output is active at any time while the other outputs are maintained at logic 0 and the output which is held active or high is determined the two binary inputs A and B.

The figure below shows the truth table for a 2-to-4 decoder. For a given input, the outputs Y0 through Y3 are active high if enable input EN is active high (EN = 1). When both inputs A and B are low (or A= B= 0), the output Y0 will be active or High and all other outputs will be low.

When A = 0 and B = 1, the output Y1 will be active and when A = 1 and B = 0, then the output Y2 will be active. When both the inputs are high, then the output Y3 will be high. If the enable bit is zero then all the outputs will be set to zero. This relationship between the inputs and outputs are illustrated in below truth table clearly.

From the above truth table we can obtain Boolean expression for the each output as

These expressions can be implemented by using basic logic gates. Thus, the logic circuit design of the 2-to-4 line decoder is given below which is implemented by using NOT and AND gates. Two NOT gates or inverters provide the complement of inputs.

A common enable line is connected to each AND gate such that when EN= 0 all the outputs are zero and if EN=1, depends on the inputs A and B, outputs are produced. Each output represents one of the minterms of the 2 input variables.

It is also possible to design 2-to-4 decoder using NAND gates as shown in figure below along with truth table. This is constructed with a principle of max terms as outputs. To generate the minterms, we have to use NAND gates which act as inverters. If both inputs are zero (A = B = 0), Y0 will be zero , if A = 0 and B= 1, then Y1 will be 1 and so on.

Therefore, only one output will be low for any combinations of inputs at a given time and all other outputs will be high. This type of decoders is available in IC forms so that 3 to 8, 4 to 16, and 5 to 32 decoders can also be made depends on the application requirement.

3-to-8 Decoder

In a 3-to-8 decoder, three inputs are decoded into eight outputs. It has three inputs as A, B, and C and eight output from Y0 through Y7. Based on the combinations of the three inputs, only one of the eight outputs is selected.

The figure below shows the truth table of a 3-to-8 decoder. Enable input is provided to activate the decoded output depends on the input combinations A, B and C. Suppose if A = B=1 and C= 0, then the output Y6 is 1 and all other outputs are zero. So from the truth table, minterms represents the each output equation and are given as

Using the above min term expressions for each output, the circuit of 3-to-8 decoder is can be implemented by using three NOT gates and eight AND gates. Each NOT gate provides the complement of the input and AND gates generates one of the minterms.

Also enable input activate the decoded output depends on the input data. The logic diagram of this decoder is shown below.

Only one of eight outputs is high at a given time for a particular input combination, that why this decoder is also called as 1-of-8 decoder. Suppose, when ABC = 011, then only AND gate 4 has all inputs high, thus Y3 is high.

Also, 3-bit binary numbers at the input is converted to eight digits at the output (which is equivalent to octal number system), that’s how; it is also called as a binary-to-octal decoder

It is also possible represent the each output equation using max terms. In such case, inversion operation is performed in the logic circuit than that of circuit with min terms. The figure below shows the truth table of 3-to-8 line decoder using NAND gates. Each output in the table gives a max term representation.

At a given time only one output is low and all other outputs will be high. For example, when A=B= 1 and C=0, then the output Y6 is zero and all other outputs are high as shown in below figure.

From the above table , a 3-to-8 line decoder is designed by using three NAND gates and three NOT gates. NOT gates generate the complement of input while the NAND gates generate max terms of each output as shown in below figure.

4-to-16 Decoder

A 4-to-16 decoder consists of 4 inputs and 16 outputs. Similar to all the decoders discussed above, in this also only one output will be low at a given time and all other outputs are high (using maxterms).

The truth table of this type of decoder is shown below. If the input to this decoder is 1000, then output Y8 will be low and all other outputs will be high as shown in figure. This will be so on for all the input combinations.

From the above truth table, a 4-to-16 decoder can be implemented by using 4 NOT gates and 16 decoding NAND gates. For decoding all possible combinations of 4 bits input, sixteen (24 = 16) decoding gates are required.

It is important to note that all the NAND gates are implemented on this circuit produce the active low outputs as shown in figure.

Since it selects one of 16 outputs based in the particular input combination, these decoders are also called as 1-of-16 decoder. And also its output represents the sixteen digits as hexadecimal number system, this type of decoder is also called as a binary-to-hexadecimal decoder.

It is possible to combine or cascade two or more decoders to produce a decoder with larger number of input bits with the use of enable input of decoder. The cascade combination of two 3-to-8 line decoder is given below figure. It consists of four inputs A, B, C and Enable E and 16 outputs Y0 to Y7.

One of the input variable is used as enable input of the first 3-to-4 decoder and this same input is complemented and connected as enable input of the second decoder. The decoder to be enabled is decided by the most significant input variable and other input variables are fed to each decoder.

When enable input is zero then the top decoder is enabled while the other is disabled. Then the top decoder eight outputs generate the minterms 0000 to 0111. Likewise, when enable is 1, the lower decoder is enabled and top one is disabled. Thus the bottom decoder outputs generate minterms from 1000 to 1111.

Applications of Decoders

Decoders are greatly used in applications where the particular output or group of outputs to be activated only on the occurrence of a specific combination of input levels. Very often these input levels are provided by the outputs of a register or counter.

When the counter or register continuously pulse the decoder inputs, the outputs will be activated sequentially. And these outputs can be used as sequencing signals or timing signals to switch the devices at particular times.

Binary to Decimal Decoder

Decoders are used to get the decimal digit corresponding to a specific input combination. A BCD number needs 4 binary digits to represent the 0 to 9 decimal digits, thus it consists of 4 input lines. It consists of 10 output lines corresponding to 0 to 9 decimal digits. T

This type of decoder is also called as a 1 to 10 decoder. For a specific input combination, the output will be activated corresponding to the decimal equivalent of the input combination.

Address Decoders

Amongst its many uses, a decoder is widely used to decode the particular memory location in the computer memory system. Decoders accept the address code generated by the CPU which is a combination of address bits for a specific location in the memory.

In a memory system, there are several memory ICs are combined and each one has their unique address to distinguish from other memory locations.

In such cases a decoder built in the memory ICs circuitry, is used to select a memory IC in response to a range of addresses by decoding the most significant bits of the systems address, thereby a particular memory location or IC is selected.

In a more complex memory system, the memory ICs or chips are arranged in multiple banks. When the microprocessor wants to access one or more bytes at a time, these banks must be selected simultaneously or individually.

In such cases more than one decoder must be activated. For that, cascaded decoders are used or most commonly decoders are replaced with programmable logic devices.

Instruction Decoder

Another application of the decoder can be found in the control unit of the central processing unit. This decoder is used to decode the program instructions in order to activate the specific control lines such that different operations in the ALU of the CPU are carried out.

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Consider in case of 8 to 3 line encoder in which, if D2 and D5 are 1 simultaneously, the encoder produces the output as 111 that means all three outputs are equal to logic 1 (as an example in case of a person operating keyboard might press a second key before releasing the first). This value does not correspond to either binary 2 or binary 5.

To overcome this problem, encoder circuit must establish a priority such that only one input is encoded at such cases. This means that whenever two inputs are equal to logic 1 simultaneously, then the encoder must prioritise the level of each input such that it produce output corresponds to highest priority input. Such an encoder is called as priority encoder.

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Priority Encoder

As said before , a priority encoder is one of the types of encoders in which an ordering is imposed to the inputs that means compared with the standard encoder, it includes the priority function.

However, this priority is based on the relative magnitudes of the inputs. Hence, the input with larger magnitude is the one that is encoded first.

Priority  encoders can select the inputs with highest priority in many practical applications. This process of selection is called arbitration.

One of the most common examples of arbitration  is that , there are numerous input devices in computer system and several of which devices attempt to supply the data to the computer simultaneously. In those cases, a priority encoder enables the input device having the highest priority among those devices trying to access the computer at the same time.

Let us see the  design  of  4 input , 8 input priority encoders.

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Simple 4-Input Priority Encoder

This Priority encoder consists of 4 inputs and three outputs. Although an encoder has 2ⁿ inputs and n outputs, it has a third output ‘V’ which is a valid bit indicator and is set to one when one or more inputs are active or equal to 1.

This valid bit is zero when all the inputs are zero which indicates that there is no valid input. On this condition, other outputs are considered as don’t care conditions and are not inspected when V is zero.

The highest will be the priority of the input with a higher subscript number according to the truth table that is most significant bit will have highest priority while the least significant bit will have low priority .

In the truth table, D3 has the highest priority and D0 has lowest priority. When D3 is active or 1, then regardless of other inputs, the output is 11. The next higher priority is D2 after D3.

The next higher priority is D2 after that D1. Thus, when D3 is 0 and D2 is 1 then regardless of other two inputs (which has lower priority), the output is 10. When higher priority inputs are zero then the output for D1 is generated and so on down the priority levels.

From the above truth table we can write the Boolean expression for the two outputs as

K-map Simplification

The above expressions for the intputs and valid output can be obtained by using the K-map simplification. Although the truth table of this encoder is shown with five rows, we can obtain 16 input combinations when each × in each row is replaced first with zero and then by one. The min terms of the two outputs can be derived as

Y1 = ∑ m (1, 2, 3, 5, 6, 7, 9, 10, 11, 13, 14, 15)

Y0 = ∑ m (1, 3, 4, 5, 7, 9, 11, 12, 13, 15)

Then from the below K-maps we obtain the outputs as

Y1 = D3 + D2

Y0 = D3 + (D2) ̅ D1

The logic diagram of 4-input priority encoder is implemented by corresponding output expressions obtained from K-map simplification. A circuit diagram of this encoder is shown below.

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8 – to – 3 Priority Encoder or Octal – to – Binary Priority Encoder

The truth table of an octal – to – binary priority encoder is shown below. This type of encoder has 8 inputs and three outputs that generate corresponding binary code. A priority is assigned to each input so that when two or more inputs are 1 at a time, the input with highest priority is represented in the output.

Suppose if the input lines D2, D4 and D7 are logic 1 simultaneously irrespective of the other inputs, only D7 will be encoded and the output will be 111. Similarly, if D3 = 1, the state of D2, D1 and D0 is irrelevant or don’t care and the output is equal to 011.

An IC 74148 is the most popularly used MSI encoder circuits for the 8 to 3 line priority encoder. The main characteristics of this encoder include cascading for priority encoding of n bits, code conversion, priority encoding of highest priority input line, decimal to BCD conversion, output enable-active low when all the inputs are high, etc.

The inputs of digital circuits often use octal code so there will be a need of entering such long binary words manually. Thus, the encoder IC is designed to achieve such operation.

The below figure shows its pin diagram and it has active low inputs and active low outputs. To handle more inputs, these ICs are cascaded by enabling input and gray outputs which are also active low lines.

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Decimal- to- BCD Priority Encoder

This type of encoder performs the same operation as that of a normal decimal to BCD encoder as encoding the decimal digits into 4-bit BCD outputs. However, it consists of an additional functionality of providing priority. That means the BCD output is produced corresponding to the highest priority of a decimal digit appearing on the inputs irrespective of all other inputs.

The figure below shows the truth table of a decimal – to –BCD encoder. This encoder has nine active low inputs representing the decimal digits from 1 to 9. According to the highest order activated input, it produces the inverted BCD code.

When all the inputs from D1 to D9 are logic 1, all the outputs are set to 1111 which is the inverse of 0000, i.e., BCD code for 0. When D9 is 1, the output is 0110, which is the inverse of 1001, i.e., BCD code for 9. This procedure is same for all the decimal numbers.

The outputs are normally high when none of the input is activated and this case corresponds to the decimal 0 inputs. Thus, when all the inputs are high, the encoder assumes the decimal 0 state as there is no D0 input.

Also, if the two inputs are activated at the same time, suppose D3 and D5 then the highest priority of these inputs, i.e., D5 is encoded as 1010 which is the inverse of 0101, that’s how this encoder is called as priority encoder.

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16 to 4 Priority Encoder

Similarly, a 16 to 4 encoder can be constructed by using six 4 to 2 encoders. Four 4 to 2 encoders are connected to the 16 inputs and the 8 outputs are again connected to the two 4 to 2 encoders , which produces 4 outputs.

Priority Encoder applications

As compared with the standard digital encoder, a priority encoder is most commonly used in several applications. A larger priority encoder is designed by cascading the several priority encoders. Therefore, this type of encoders is used to reduce the number of connections required in a particular application in which there are multiple inputs are present.

Keyboard Encoders

Assume that a QWERTY keypad is interfaced with microcomputer and hence computer has to read the 104 keys of the keyboard such that at any time it would read only one key pressing as either High or LOW.

It is not possible to connect all these 104 connections directly to the computer (if it is of less configured), however it is a more effective way to connect them by the use of priority encoder. By using this encoder, each character or key is encoded into a standard ASCII code of 7 bits (0-127 decimal) from

all these 104 keys or individual buttons. Then it inputs 7-bit BCD code to the computer. One of such type of keyboard encoder is 20 key, 74C923. And also these encoders provide the facility of priority such that when two keys are pressed at the same time, it gives the highest priority inputs.

Positional Encoders

A magnetic positional control is another common application of priority encoders. Such control is used in robotic arm positioning and ship navigations. In such cases, encoder converts the rotary or angular position of a compass to a digital code. Then this code is input to the computer so that the navigational data is provided.

Below figure shows the simple compass encoder that converts the 8 positions to 3 bit output. For this type of input –output configuration, a 74LS148 IC is used which is an 8-to-3 line priority encoder. For indicating the compasses angular position, generally reed switches and magnets are used.

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It encodes the given information into a more compact form. In other words, it is a combinational circuit that performs the opposite function of a decoder.

These are mainly used to reduce the number of bits needed to represent given information. In digital systems, encoders are used for transmitting the information. Thus the transmission link uses fewer lines to transmit the encoded information.

In addition, these encoders are used for encoding the data which is to be stored for later use as it facilitates fewer bits storing over the available space. Let us discuss various types of binary encoders.

Binary Encoder

A binary encoder has 2n input lines and n output lines, hence it encodes the information from 2n inputs into an n-bit code. From all the input lines, only one of an input line is activated at a time, and depending on the input line, it produces the n bit output code.

The figure below shows the block diagram of binary encoder which consists of 2n input lines and n output lines. It translates decimal number to binary number.

The output lines of an encoder correspond to either true binary equivalent or in BCD coded form of the binary for the input value. Some of these binary encoders include decimal to binary encoders, decimal to octal, octal to binary encoders, decimal to BCD encoders, etc.

Depending on the number of input lines, digital or binary encoders produce the output codes in the form of 2 or 3 or 4 bit codes.

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4 – to – 2 Bit Binary Encoder

The block diagram and truth table of a 4 input encoder is shown in below figure. The truth table consists of four rows , since , it is assumed that only one input is the value of 1 then the corresponding binary code associated with that enabled input is displayed at the outputs.

It is to be observed from the table is the output Yo is 1 when either input w1 or w3 is 1, also the output Y1 is set to 1 when either input w2 or w3 is 1.

The output from 4-to-2 encoder is generated by the logic circuit implemented by a set of OR gates as shown in below. In the figure a, the output of the encoder is same if the input activated is the Io input (Io = 1) or if no input is activated i.e., all the inputs are zero.

This causes ambiguity in the encoding output. To avoid this ambiguity, a valid encode output can be added as an additional output, so this output assumes a value 1 when Io is equal to 1.

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Decimal to BCD Encoder

This type of encoder usually consists of ten input lines and 4 output lines. Each input line corresponds to the each decimal digit and 4 outputs correspond to the BCD code.

This encoder accepts the decoded decimal data as an input and encodes it to the BCD output which is available on the output lines.

The figure below shows the basic logic symbol of decimal to BCD encoder along with its truth table. The truth table represents the BCD code for each decimal digit.

From this we can formulate the relationship between the BCD bit and decimal digit. It is important to note that there is no explicit input line for decimal zero. When this condition occurs, i.e., decimal inputs 1 to 9 all are zero, then the BCD output is 0000.

From the above table, we get the expressions as

Y3 = D8 + D9

Y2 = D4 + D5 + D6 + D7

Y1 = D2 + D3 + D6 + D7

Y0 = D1 + D3 + D5 + D7 + D9

From the above expressions, the decimal to BCD encoder logic circuit can be implemented by using set of OR gates as shown in below figure.

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Octal to Binary Encoder

An octal to binary encoder consists of eight input lines and three output lines. Each input line corresponds to each octal digit and three outputs generate corresponding binary code.

In encoders, it is to be assumed that only one input is active or has a value 1 at any given time otherwise the circuit has no meaning. The figure below shows the logic symbol of octal to binary encoder along with its truth table.

From the above table, the output Y2 becomes 1 if any of the digits D4 or D5 or D6 or D7 is one. Thus, we can write its expression as

Y2 = D4 + D5 + D6 + D7

Similarly, Y1 = D2 + D3 + D6 + D7 and

Y0 = D1 + D3 + D5 + D7

Also it is to be observed that D0 does not exist in any of the expressions so it is considered as don’t care. From the above expressions, we can implement the octal to binary encoder using set of OR gates as shown in figure below.

There is ambiguity in the octal to binary encoder that when all the inputs are zero, an output with all 0’s is generated. Also, when Do is 1, the output generated is zero. This is a major problem in this type of encoder. This can be resolved by specifying the condition that none of the inputs are active with an additional output.

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Digital Encoder Applications

Encoders are very common electronic circuits used in all digital systems. In case of pocket calculators, these are used to translate the decimal values to the binary in order to perform the binary functions such as addition, subtraction, multiplication, etc.

These are also used to generate the digital signals in response to the movement which are classified into shaft encoders and linear encoders. Let us discuss keyboard applications of encoders in brief.

Keyboard Encoder

This type of encoder function is to generate the binary code corresponds to the alphanumeric character key depressed on a keyboard. The below figure shows a keyboard encoder used to encode the 10 decimal digits in BCD code by using a diode matrix. In this circuit, BCD data are stored in the S-R flip-flops.

When a key corresponding to one of the decimal digits is pressed, the selected diodes are forward biased by a positive voltage, and these are connected to the set and reset terminals of S-R flip-flops. The diode arrangement is made in such a way that each flip-flop set or resets so as to produce the 4 bit BCD code.

Suppose if key corresponds to decimal digit 7 is pressed, the diodes which are connected to the S inputs of Q4, Q2 and Q1 are forward biased, also the diode which is connected to the R input of Q8. Therefore, the output BCD code is 0111.

From the logic diagram of the encoder, it is to be observed that the diode configuration at each S and R input is essentially a diode OR gate. This type of diode matrix encoders is used in printed circuit boards on many electronic devices having keyboards as user data interface.

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